This invention is related to our co-pending Application Serial No. 07/138,184 filed 28 Dec. 1987 and now U.S. Pat. No. 4,833,639 entitled HIGH SPEED ANALOG MULTIPLIER-ABSOLUTE VALUE DETECTOR.
2. Field of the Invention
The present invention is related to phase detectors for high speed phase locked loops of the type employed in quadrature phase shift key (QPSK) receivers. More particularly, the invention relates to a high speed computational circuit for generating the sum or difference of the absolute value of two or more signals and may be employed as a phase detector for multi-phase QPSK demodulating receivers.
3. Description of the Prior Art
Our co-pending Application Serial No. 07/138,184 shows and describes a high speed analog multiplier which is capable of being operated as an absolute value detector. Prior to the invention described in this co-pending application, analog multipliers had been limited to speeds or frequencies of around 25 megahertz before distortion rendered the output unusable. The high speed analog multiplier in our co-pending application avoided the limitations on operable frequencies imposed by the use of commercially available diodes multipliers.
Prior art phase detectors for multi-phase shift key (PSK) receivers also employ commercially available diodes and operational amplifiers which have limited the operational frequency of these prior art phase detectors to about 25 megahertz. Prior art multi-phase detectors employed analog multipliers having cross-channel inputs which produce complex cross-channel modulated output products that have limited the operational frequency of this type of multiplier in a cross-channel mode used to approximately 10 megahertz.
It would be extremely desirable to provide a high speed multi-channel phase detector which is capable of speeds of about 400 megahertz employing commercially available semiconductor devices and having speeds up to 5 gigahertz employing gallium arsenide semiconductor devices without distortion.